This invention is related in general to computing circuitry and in particular to circuits for detecting trailing zeros in numbers.
In performing numerical computations it is frequently necessary to multiply two numbers. One or both numbers to be multiplied may contain a number of trailing zeros. This is most common in floating point arithmetic where a number is represented in three parts: a sign bit indicating whether the number is positive or negative, an exponent and a fraction portion of the number. The fraction portion is usually normalized by shifting the fraction to the left so that the most significant bit of the fraction portion is non-zero. If the non-zero part of the fraction portion is short compared to the length of the fraction portion, the portion will contain many trailing zeros. When two numbers are multiplied the exponent portions of the two numbers in floating point format are added. The fraction portions of the two numbers are then multiplied. If the fraction portion of the multiplier contains a long string of trailing zeros, a large number of multiplication steps would be required to multiply the respective zero portions. This seriously slows down the operation of the computing system.
In conventional multiplier systems, where two numbers to be multiplied are not represented in floating point format, multiplication steps would still be necessary to multiply the multiplicand by the zero portion of the multiplier. It is therefore desirable to provide circuitry for detecting trailing zeros of numbers to be multiplied so that the zero portions of such numbers may be skipped over.
In U.S. Pat. No. 4,276,607 Wong discloses a multiplier circuit for detecting and skipping over trailing zeros of the multiplier. In Wong's system a floating point number of 64 bits in length is represented by concatenating four words together each 16 bits long. The four words are supplied sequentially to a register and a non-zero detector at the same time. When a particular word is detected to contain at least one non-zero bit the word number corresponding to the non-zero word is registered in the register. The lowest order word among the four words having non-zero content is determined.
In Wong's multiplier circuit, the non-zero content of the words of each number is determined sequentially which requires a significant amount of time which may offset a significant portion of the time saved by skipping over trailing zeros in the multiplier. Thus, Wong's system as disclosed in U.S. Pat. No. 4,276,607 is not entirely satisfactory.